Your quick summary of news from the server room
Gotta hand it ’em … an Intel FPGA PAC D5005
Roundup Register vultures and readers alike are off on summer vacation, or attending hacker comic con in the desert, right now, and yet the wheels of news keep turning in the data center world. So, for those still logged in, here’s a quick summary of announcements from the server room this week.
- Xilinx has added the U50 card to its Alveo family of data-center accelerators. The 75W U50, a single-slot, half-height, half-length PCIe 4.0 device, is designed to be dropped into servers to speed up, in hardware, specific workloads offloaded by the host’s general-purpose processors.
Under the hood, the U50 features an UltraScale+ FPGA, 8GB of 460GB/s high-bandwidth memory (HBM2), 100GbE network connectivity, and CCIX as well as the aforementioned PCIe 4 interfaces. The idea is, you configure the on-board FPGA to handle whatever workloads you want to throw at the thing: the programmable array has 872,000 lookup tables, 1,743,000 registers, and 5,952 DSP slices, with 28MB of 24TB/s SRAM.
It is due to go on sale by Fall 2019, and is being shown off at the Flash Memory Summit in Silicon Valley right now, our storage sister site, Blocks and Files, reports.
- Speaking of FPGAs, funnily enough, Intel is now said to be shipping its Programmable Accelerator Card (PAC) D5005 that features a high-end Stratix 10 SX programmable gate array. The gear will debut in HPE ProLiant DL380 Gen10 servers.
Like the U50, the D5005 is intended to be configured to accelerate specific tasks and algorithms in hardware; this is due to more and more folks wanting specialist workloads, such as machine learning, physics simulators, and similar number crunching, handled by dedicated processing units that can guarantee high levels of performance, to take the strain off general-purpose CPUs that are there to direct the flow of data and deal with application logic.
The D5005 is aimed at 2U servers, and is a full-height, three-quarter-length PCIe card. It draws up to 215W, includes 32GB of DDR4 RAM, provides two 100GbE networking ports, requires two x16 PCIe 3.0 slots, and features 2.8 million logic elements, as well as other bits and pieces including a smaller FPGA for remotely managing the hardware. The main Stratix 10 SX includes a quad-core Arm Cortex-A53 CPU cluster for running control software.
For a deeper dive into the hardware, check out our supercomputing sister site, The Next Platform.
- And speaking of Intel, Chipzilla has promised to ship in the first six months of 2020 14nm 56-core Xeon server-grade processors code named Cooper Lake. These follow on from the 56-core Xeon Platinum 9200 series teased earlier this year.
The difference, it seems, is that Cooper Lake is basically a step up from what was teased before: it will draw less power and sport higher memory bandwidth with eight channels rather than seven; will be socketed rather than soldered directly onto boards like the 9200 family, and fit motherboards designed for 10nm Ice Lake Xeons; will use a three-die package rather than a single monolithic die; and support things like bfloat16 designed to accelerate AI math.
Intel is bragging about this because this week AMD is due to unveil its 7nm 64-core Zen-2-based second-generation Epyc server processor code-named Rome, which is set to at least take some of the wind out of Chipzilla’s sails (or should that be sales).
- Nvidia has revealed more details about its GPUDirect Storage mechanism that allows its graphics processors to efficiently and directly access data held in NVMe-connected storage via PCIe, rather than bouncing the information back and forth through the system RAM which is a pain.
The GPU giant last spoke of GPUDirect Storage in March, and now it has shared more info, including benchmarks and other testing, on this unreleased work-in-progress technology. You can also catch a summary of the approach on Blocks and Files. ®