Early details of the specifications for PCIe 7.0 are out, and it’s expected to deliver data rates of up to 512 GBps bi-directionally for data-intensive applications such as 800G Ethernet.
The announcement from the The Peripheral Component Interconnect Special Interest Group (PCI SIG) was made to coincide with its Developers Conference 2022, held at the Santa Clara Convention Center in California this week. It also marks the 30th anniversary of the PCI-SIG itself.
While the completed specifications for PCIe 6.0 were only released this January, PCIe 7.0 looks to double the bandwidth of the high-speed interconnect yet again from a raw bit rate of 64 GTps to 128 GTps, and bi-directional speeds of up to 512 GBps in a x16 configuration.
Those looking forward to the extra bandwidth should be aware that the PCI-SIG technical workgroups have only just begun development work on the specifications, which are not set to be completed and released to members until 2025.
Meanwhile, the first shipping products compatible with the PCIe 6.0 specs are not expected until later this year, and PCIe 5.0 devices only really started to come to market during 2021.
Few processor chips from the likes of Intel and AMD even support PCIe 5.0 I/O lanes at this stage, let alone PCIe 6.0.
Some of Intel’s Alder Lake CPUs have PCIe 5.0, while the Sapphire Rapids versions of its Xeon server chips are expected to have it later this year. AMD’s Epyc server chips still have PCIe 4.0, and are not expected to have PCIe 5.0 until versions based on the next-generation Zen 4 cores are available.
However, the PCI-SIG is planning for the future, and PCIe 7.0 is being developed for the requirements of data-intensive applications such as artificial intelligence and machine learning, which may call for high-speed plug-in accelerators, plus 800G Ethernet adapters and hyperscale datacenters.
PCI-SIG president Al Yanes said that the forthcoming specifications continued the PCI-SIG’s 30-year commitment to “push the boundaries.”
“As PCIe technology continues to evolve to meet the high bandwidth demands, our workgroups’ focus will be on channel parameters and reach and improving power efficiency,” he said.
Of the few details PCI-SIG has so far disclosed, PCIe 7.0 is set to feature PAM4 (Pulse Amplitude Modulation with 4 levels) signalling, which was introduced for PCIe 6.0. It is also expected to delivery greater power efficiency, and maintaining backwards compatibility with all previous generations of PCIe technology is the top priority. ®